1. Field of the Invention
The embodiments of the invention relate to circuit design and more particularly to simulating models of parasitic effects in technologies which span multiple fabrics. Although embodiments of the invention are suitable for a wide scope of applications, it is particularly suitable for automatically, under the guidance of user-defined rules, extracting layout objects from a layout spanning multiple fabrics, recognizing custom design patterns in the layout, binding the layout objects to specialized solvers to generate models of parasitic effects, and simulating combinations of the models arising from layout objects which span multiple fabrics.
2. Discussion of the Related Art
In general, an electronic system include a plurality of integrated circuit chips (IC) for performing various electronic functions. Each IC includes many electronic components (e.g. transistors, diodes, inductors, capacitors, inverters, logic gates, multiplexers, etc.) interconnected in a prescribed manner to respond to input electrical signals and produce other electrical signals according to the desired electronic function performed by the IC. The electronic system may also include one or more package and one or more board, such as a printed circuit board (PCB). Each of the die, the board and the package constitutes a fabric for exchanging electrical signals between the various electrical components.
The electronic components or objects in the electronic system are interconnected with signal paths that carry electrical signals into and out of an IC die through a package substrate to the package input/output connectors across the multiple fabrics. The signal path traverses multiple fabrics through package balls, wirebonds, vias to interconnect the electronic components.
FIG. 1 shows a block diagram of an RF system according to the related art. Referring to FIG. 1, a RF system 100 includes a microprocessing unit 110. The microprocessing unit 110 may be provided in a die. The microprocessing unit 110 may be connected to one or more capacitor 120 provided on a board, such as a PCB board via one or more wirebond 112. The microprocessing unit 110 may also be connected to additional electrical elements through a via 140. The interconnection from the microprocessing unit 110 to the via 140 may include a RF path 116. The microprocessing unit 110 may also be connected to a rectangular inductor 130 on the PCB. The rectangular inductor 130 may itself be connected to a capacitor 150 via a transmission line 132.
The related art RF system of FIG. 1 also includes a RF coupler 160 provided on the PCB. The RF coupler 160 is connected to a capacitor 170 via an interconnection 162. The RF coupler 160 is also connected to an inductor 180 on the PCB via an interconnection 164.
The design of an electronic system, such as the RF system 100 of FIG. 1, may involve multiple phases with particular requirements. For example, during an exploration phase, the designer of an electronic system may use quick design tools to obtain initial models for an RF signal path, such as RF path 116. The designer may use more accurate but slower design tools to refine the initial models or obtain more accurate models at a verification phase. Moreover, a design team may prefer to use one or more specific solver to model specific physical structures in an electronic system.
There are many tools targeted to verification of circuits, but there is a tradeoff between specialized tools targeted towards verification of specific elements of circuits and general tools targeted towards verification of a broader range of elements and entire circuits. Verification tools addressing entire circuits are often ill-suited to the verification of specialized components of a circuit. For example, a circuit verification tool may be both inaccurate and slower than a more specialized verification tool when faced with a specialized component.
These structures cannot all be modeled optimally with a single electromagnetic field solver, but specialized solvers exist which are capable of modeling these specific structures more quickly or with greater accuracy. For example, a specialized wirebond solver may be required for accurately modeling the behavior of the interconnection between the microprocessing unit 110, the capacitor 120 and the wirebond interconnection 112. Similarly, a specialized RF solver may be required to model the behavior of the interconnection from the microprocessing unit 110 through the via 140. Moreover, the designer may want to use a customized algorithm for modeling the transmission line 130 between the rectangular inductor 130 and the capacitor 150.
A portion of the layout for an electronic system need be extracted to use specialized solvers for particular elements of the electronic system. For instance, to use a specialized wirebond solver for portion of the RF system 100 of FIG. 1, a designer needs extract the layout of the wirebond portion of the RF system 100 including the microprocessing unit 110 from the corresponding die, the capacitor 120 from the PCB and the wirebond interconnection 112. Similarly, to use a specialized RF solver for the RF path from the RF system 100, the designer needs to extract the layout of the elements interconnected by the RF path including the microprocessing unit 110, the via 140 and the connector 116. To use a customized algorithm for modeling the transmission line 132, the designer needs extract the layout of the elements of the RF system 100 that are interconnected by the T-line 132 including the rectangular inductor 130 and the capacitor 150.
Simulation of behaviors of a circuit may be done using models created by solvers. If various pieces of a circuit were solved by different solvers, the models must be combined to simulate behaviors of portions of the circuit which encompass pieces modeled by different solvers. However, each solver may have its own format, and each simulator may also have its own format.
According to the related art, models generated by different solvers are combined or stitched manually to provide the output of a modeled component to the input of another modeled component, and imported into a simulator or simulation test bench. However, manual stitching of models is error prone.
Moreover, the models generated by the solvers are generally in one or more standard formats. However, the input to individual solvers may be in various formats. The manual translation of a solver's output in a format compatible with another solver's input is time-consuming and also error prone.
Furthermore, changes made to the layout in one or more of the fabrics require rerunning the extraction process, which is also time-consuming and error prone in a manual environment because of the many combinations of models required for the simulator or simulation test bench.
Circuits which are embedded in multiple fabrics present additional challenges to verification and simulation. Specialized tools may be able to extract and solve objects from any single fabric, but there is a need to extract objects from multiple fabrics, create models of objects which span multiple fabrics, and to simulate behaviors of circuits such as RF circuits which span multiple fabrics. There may also be instances where the layout objects spanning multiple fabrics may be designed with a specific geometry, and it would be desirable to recognize those geometries for potential use with specialized solvers targeted towards objects with those geometries. The current approach used to solve signal paths which pass through multiple fabrics is to manually identify special geometries from the multiple fabrics and to generate models for simulation which are stitched together manually for use in simulation.